Introduction to EAGLE – Part 1 – Control panel
This article is part of a tutorial dedicated to EAGLE. The reader may consult the other parts of the tutorial by following this link: Introduction to EAGLE
Eagle stands for Easily Applicable Graphical Layout Editor. It is an electronic CAD software manufactured by CadSoft Computer GmbH, a German company, since 1988. This software is provided with, among other, a schematic capture editor, a PCB (Printed Circuit Board) layout editor, an auto-router, a Computer-Aided Manufacturing (CAM)… It supports Windows, Linux and Mac OS X. This tutorial has been prepared under version 6.5.0 / Ubuntu 12.04 LTS
Control panel
When EAGLE is started, the following window appears on the screen,this is the control panel, the EAGLE starting window.
On the left hand side of the window the user manage existing and new projects and can get an overview about the libraries and settings :
- Libraries: this entry lists libraries of components, each component is composed of a schematic and a footprint linked together.
- Design Rules: the user can tune the parameters relevant to the board and its manufacture.
- User Language Programs: this is C-like programs that can be used for a variety of tasks. It can be used, for example, to modify your project and automize certain tasks.
- Scripts: the user can execute sequences of commands that are stored in a script file. It provides the ability to customize the program according to your own wishes (assign keys,
load pc board shapes, change colors…) - CAM Jobs: CAM stands for Computer-Aided Manufacturing. It generates output data for the manufacturing tools (for exemple exporting Gerbers files which is the most used professional format).
- Projects: this entry lists the examples and projets. When a new project is created, it is automaticaly added in the tree.
The Arduino MEGA2560 board has been designed with EAGLE. It is provided within the examples:
Directories
Basicaly, EAGLE stores all the projects and necessary files in the same main folder and creates subfolders to differenciate each projet. In the main menu bar, select Option > Directories:
The following interface allows the user to configure directories. $EAGLEDIR represents the path to the main folder (on my installation it is located in /home/username/eagle-6.5.0/). When a new project is created, a new folder is automatically added in $EAGLEDIR/projects/ . The user can specify several folders. It is possible, for example, to have the default libraries available on a network server, and the personal projects in private local folders.
Before continuing check that the folder for libraries is configured with the following path: $EAGLEDIR\lbr.
Libraries
On the left hand side of the control panel, click on Libraries to develop the tree and select the library 74xx-eu.lbr. This library is dedicated to TTL Devices (74xx Series from Texas Instruments). Select a device, on the right side the symbol and footprint appear:
New project
To create a new project, select File > New > Project :
A new project is automatically added on the left hand side of the window under the branch Project/eagle. Enter you project name, for example FirstPCB :
Right click on the project and select New > Schematic.
A new window is automatically open, this is the Schematic Editor:
Introduction to EAGLE – Part 2 – Schematic editor
This article is part of a tutorial dedicated to EAGLE. The reader may consult the other parts of the tutorial by following this link: Introduction to EAGLE
In this tutorial the reader will be guided to create a simple PCB, first lets start by creating the schematics.
Workspace
Before starting the schematic, lets insert a frame containing title, date, author … On the vertical tool bar located on the left side of the window, click on the ADD icon. The ADD action allows to add new item in the design. It is largely dedicated to the insertion of new components.
A window pops up and display all the available libraries. In the search entry located at the bottom left of the window, type “frame” and confirm with the Enter key :
The list of libraries is now limited to entries containing the string “frame” in there title or description. Select the A4L-LOC which is a DIN A4 Landscape frame and click OK. The frame is now attached to the cursor, place the frame in order to align the bottom-left corner of the frame at coordinates 0,0. Coordinates are displayed in the upper left corner of the working area. The origin is also display in the working area with a small dotted cross. When the frame is placed, left click with the mouse and hit twice the “Esc” key to exit.
Save your design and change the view by clicking on “Zoom to fit”. You should now have a general view of your future design.
Click on the grid icon:
The grid setting window appears, in this window, you can set the grid parameters (size, style, etc.). Set display “On” and click “OK”. Your workspace is prepared for the schematic and should look like this:
Adding symbols
Click to the ADD icon as explained previously for adding the frame. EAGLE is provided with a large number of librairies, and the user can enter one or more search patterns in the search field by using special characters (wild cards) ‘?’ and ‘*’:
- * is a search pattern that can be replaced by one or several characters. For example *555 will provide all the entries ending by 555. 555* will provide all the entries beginning by 555 and *555* will provide all the entries containing 555.
- ? is a search pattern similar to ‘*’, excepted that it can only be replaced by a single character.
It is usefull to remember that when you add a device, right click rotate and left click place the symbol. Once a symbol is placed, several operations are still possible :
Search and add the following components in your design (the belonging library and package is mentioned in brackets) :
| COMPONENT | LIBRARY | DEVICE | PACKAGE |
|---|---|---|---|
| 555 timer | st-microelectronics | NE555 | DIL-08 |
| Resistor | rcl | R-EU | 0204/7 |
| Polarized capacitor | rcl | CPOL-EU2,5-6E | E2,5-6E |
| Capacitor | rcl | C-EUC1206 | C1206 |
| Screew terminal | con-ptr500 | AK500/2 | AK500/2 |
| 5mm LED | led | LED5MM | LED5MM |
| VCC supply symbol | supply2 | VCC | – |
| GND supply symbol | supply2 | GND | – |
Note that, even if VCC and GND are provided for convience and are not real components, they can be found in the libraries. Add and place your components in order to get the following arrangement:
Adding connections
The electrical connections have to be drawn with the NET tool (or the bus tool for buses). The WIRE tool also draw lines, but it is not dedicated to electrical connections, it belongs to the drawing tools (text, circle, arcs…).
Once the NET tool is selected, add a connection by clicking on the first pin to connect. Place the cursor on the second pin or junction, and right click without moving the mouse : the wire bend style will automaticaly change. It can also be done by selecting one of the wire bend style icon:
Place the connection according to the following schematic. This is a very simple NE555-based LED blinker:
Component name and value
The following icon (NAME) allows the user to change a component name :
In the same way, the VALUE icon allows the user to add or modify the component value (when applicable):
Rename and set values of each symbol according to the following illustration:
Check errors
Once your schematic is finished, it is safe to use the ERC (Electric Rules Check) tool. It can detect many mistakes in the design (wrong connections, non compatible junctions …)
.
A new window pops up, and displays four warnings:
The first one says that the pin 8 of the NE555 is called VCC+ and is connected to VCC. The three others say that the frame, the LED and the screw terminal don’t have values. As none of this four warning is an error, the four errors can be approved. The dialog box should now display zero error, zero warning and four approved:
Generating board
When the schematic is finished and checked, the board can be created. Click on the following icon to generate the board and launch the board editor.
EAGLE may ask you to confirm the creation of a new board from your schematic, answer yes and the PCB is automatically prepared for routing:
Introduction to EAGLE – Part 3 – Board editor
This article is part of a tutorial dedicated to EAGLE. The reader may consult the other parts of the tutorial by following this link: Introduction to EAGLE
It is here assumed that the reader had studied the part 2 and that the schematic has been processed. The board editor should now look like this illustration:
Forward and backward annotation
Check that the schematic editor and the board editors are open simultaneously. Save both designs and close the board editor. The schematic editor display the following message : “Forward and backward annotation has been severed !”:
A key element is that EAGLE maintains the link between the schematics and the PCB. When a modification is perfomed in the schematic, the PCB is immediatly updated (forward annotation). In the same way when the PCB is modified, the schematic is updated accordingly (backward annotation). It prevents the project from splitting into incompatible parts. The downside is that the designer have to consider it while working.
Workspace
The board editor environment is very similar to the schematic editor (user interface arrangement is almost the same). As it was done for the schematic editor, display a grid of 50 mils in the board editor. Now select the WIRE tool to draw the board outline. Above the working area an horizontal menu bar is displayed. This is the wire properties. Set the layer to 20 (Dimension) and select a width of 10 mils. Note that the unity of the editor is set by the unity of the grid.
Left-click on the origin of the working area (coordinates 0,0), now click at coordinates 1600,1000 and finaly double click anew on the origin (right click at each point while defining the outline changes the wire bend style). The board outline should now be visible in grey:
It is convinient to remember that the mouse wheel allows you to zoom in and out and the middle button allows you to drag your design to another place (middle button has to be maintained pressed while moving the mouse).
Placement
As for the schematic editor, the MOVE tool is used for moving components. The view displayed in the board editor is a top view of the PCB. Item drawn with the red color are located on the top side (component side) and item drawn in blue are located on the bottom side (copper side). To transfer a component on the other side, use the MIRROR tool. Select the tool, and click close to the origin (white cross) of the component to transfert. Place C2 on the bottom side, and C3 on the top side.
As for the schematic editor, when moving a component left-click places the component, right-click perfoms a rotation. While placing the components, it is possible to update the ratsnets (i.e. calculate the shortest airwire for each connection) by clicking on this icon:
Place the components according to the following arrangement and update the ratsnet.
Routing
Routing consists now in transforming the airwires into routed copper-made tracks. It is done with the help of the tool ROUTE:
To create a new track, select the routing tool and click on the airwire you want to route. The track appears while moving the cursor. Right-click change the wire bend style as for nets in the schematic editor. Double-click ends the operation. By changing the layer above the upper left corner of the working area while routing, it switchs the track from one side to another and automaticaly add a via if necessary. You can save a lot of time using the middle button of the mouse to switch from ont to another layer.
The inverse tranformation (from tracked route to airwire) is not done with the DELETE tool. This action removes the connection. While forward and backward annotation is enable, deleting a connection is not possible from the board editor; it must be done in the schematic editor. To unroute a track, use the RIPUP tool:
The inverse tranformation (from tracked route to airwire) is not done with the DELETE tool. This action removes the connection. While forward and backward annotation is enable, deleting a connection is not possible from the board editor; it must be done in the schematic editor. To unroute a track, use the RIPUP tool:
It is usefull to remember that selecting an airwire with RIPUP converts all adjacent routed wires and vias into airwires, up to the next pad, smd or airwire. Thus, by left-clicking twice on a track it quickly unroutes the connection. Tracks and vias can be moved with the MOVE command. Selecting a wire segment near an end point will move the end point of the track. Selecting the wire in the middle will move it in parallel. Note that to move components there origins have to be displayed (layer 23 (tOrigins) and 24 (bOrigins) for components respectively on top and bottom layers).
With the SPLIT command you add a bend in a wire. It is usefull to push or modify an existing track:
With the SPLIT command you add a bend in a wire. It is usefull to push or modify an existing track:
Route the board according to the following illustration (track width is 50 mils):
Modifying the board
The CHANGE tool allows you to change any property of your design. When selecting the CHANGE tool, a contextual menu appears with the list of properties:
Select WIDTH > 10 and click on any track of your design. The track width is modified. You can reverse the action with the UNDO command (Ctrl-Z). Note that modifying component names or values can’t be done with the CHANGE tool, it must necessary be done with the NAME and VALUE commands as in the schematic editor. Set the value of resistor R3 from 680 to 470 and check in the schematic that the value has been back annotated:
Perform the inverse action from the schematic editor and check that the board has been updated. Note that when you apply and action to an object that is too close from another, the software is enable to guess which is concern. In this situation, a single object is highlighted and a right-click allows to switch to the another potentially concerned object. Left-click finally applies the action to the current highlighted object.
Design rule check
Before manufacturing the PCB, it is safe to check the design thanks to the DRC (Design Rule Check). First click on the DRC icon.
The DRC configuration window appears. The designer can specify its own project design rules. Once the rules are configured, click the CHECK button to start the Design Rule Check. When there is no error, a message is simply display at the bottom of the board editor. If existing errors are found, a window appears:
Here two errors are detected. The hole size of the vias is too small according to the design rules. By selecting one of the error, the problem is highlighted in the design:
With the CHANGE command, change the drill diameter of the vias from 23.62205 to 27.55906. Check again your design, you should, at the bottom-left corner of the window, have the message : “DRC: No errors”. Your design is ready for manufacturing.
Click here to return to the main summary
Introduction to EAGLE – Adding mounting holes to a PCB
This article is part of a tutorial dedicated to EAGLE. The reader may consult the other parts of the tutorial by following this link: Introduction to EAGLE
VIA versus HOLE
There is two ways (via or hole) to add a mounting hole in a PCB and the difference between the VIA and the HOLE tools can be confusing.
A via is composed of a hole and a copper area surounding the hole. But the main différence between vias and holes is the electric connection made between layers by the via. The HOLE tool just place a hole in the design without copper or connection. Depending on what the mounting hole is made for, you may add a VIA or a HOLE. The following capture shows the difference between vias and holes. On the left side of the PCB, holes has been added, and on the right side of the board, two vias has been placed.
As it is illustrated on the following figure, vias are isolated from copper pour:
Hole diameters
Regardless the selected tool, the hole diameter has to be defined. The PCB editor is generaly configured in mils (or inchs) and the fastening specification is generaly provided in millimeters. The following table is a quick references of most used diameters.
| [MIL] | [MM] |
|---|---|
| 19.68504 mils | 0.5 mm |
| 23.62205 mils | 0.6 mm |
| 27.55906 mils | 0.7 mm |
| 31.49606 mils | 0.8 mm |
| 35.43307 mils | 0.9 mm |
| 39.37008 mils | 1.0 mm |
| 43.30709 mils | 1.1 mm |
| 47.24409 mils | 1.2 mm |
| 51.1811 mils | 1.3 mm |
| 55.11811 mils | 1.4 mm |
| 59.05512 mils | 1.5 mm |
| 62.99213 mils | 1.6 mm |
| 78.74016 mils | 2.0 mm |
| 86.61417 mils | 2.2 mm |
| 110.23622 mils | 2.8 mm |
| 125.98425 mils | 3.2 mm |
If the value is not listed, check this link : Distance converter.
Click here to return to the main summary
Introduction to EAGLE – Adding copper pour
This article is part of a tutorial dedicated to EAGLE. The reader may consult the other parts of the tutorial by following this link: Introduction to EAGLE
Copper pour
The copper pour outline is drawn with the POLYGON command:
Select the POLYGON tool. If the copper pour needs to be attached to a net, you can enter the net name straight after selecting the tool and validate with the Enter key:
It is still possible to modify the connection by right clicking on the edge of the polygon, in the contextual menu, select NAME. In the pop-up window, replace GND by the label of the new connection. This is also useful to check that the connection has been successfully done.
Left-click to draw polygon edges and double click to close the polygon. Once the outline is drawn, it appears in dotted lines:
Click the RATSNETS to calculate the copper pour:
The board should be updated. When the board is modified, the copper pour is not always recalculated. It is usefull to remember that RATSNETS force the calculation of the copper pour.
Board outline conflict
According to your design check rules, the copper pour may sometime not reach the board outline:
This can be solved by setting the distance between the copper pour and the dimension layer equal to zero. Click on DRC, select tab Distance and set the distance equal to 0:
Attaching a net
Before attaching a net to the copper pour, it is sometime usefull to unroute the existing tracks already routed. Use the command RIPUP, for example “RIPUP GND”, to unroute all the tracks named GND.
To add or change the copper pour net attachment, select the NAME command and click on the polygon. A window pop up and the user can modify or specify the name of the copper pour. When the name is the same as an existing track (for example GND), an electric connection is automaticaly created between the track and the copper pour. On the following board, the copper pour is connected to the groung:
To add or change the copper pour net attachment, select the NAME command and click on the polygon. A window pop up and the user can modify or specify the name of the copper pour. When the name is the same as an existing track (for example GND), an electric connection is automaticaly created between the track and the copper pour. On the following board, the copper pour is connected to the groung:
Remove copper pour
To definitively delete the copper pour, since the polygon is attached to the copper pour, delete the polygon. To temporary remove or hide the copper pour, select the RIPUP tool and click on the polygon. It removes the copper pour while keeping the polygon (dotted lines). Click RATSNETS again to recalculate the copper pour.
Introduction to EAGLE – Understanding layers
This article is part of a tutorial dedicated to EAGLE. The reader may consult the other parts of the tutorial by following this link: Introduction to EAGLE
Each layer in EAGLE is dedicated to a given function. Placing each item in the appropritaed layer is highly recommanded. This article presents each layer and describes it functionality. The famous Arduino MEGA 2560 board is taken as example. Note that the picture is not exactly identical to the PCB, but is quite enough to understand each layer:
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Layer 1 – Top
The first layer contains the top side tracks and the top side copper pour (if used).
Layer 2 to 15 – Route
This is the inner layer tracks (only for multilayer PCB).
Layer 16 – Bottom
This layer contains the bottom side tracks and the bottom side copper pour (if used).
Layer 17 – Pads
This layer contains the through-hole pads.
Layer 18 – Vias
This layer contains the through-hole vias.
Layer 19 – Unrouted
This layer contains the unrouted tracks, i.e. the airwires (rubberbands). Here almost all the board is routed, there is just a few unrouted tracks:
Layer 20 – Dimension
This layer contains the board outlines and circle for holes.
Layer 21 – tPlace
This layer contains the top side silk screen. It usualy contains the component outlines. Care must be taken not to cover any ares that have to be soldered. It is also possible to create additional and rather betterlooking silk screen for documentation purposes in layer 51, tDocu. This may indeed cover soldered areas, since it is not output along with the manufacturing data.
Layer 22 – bPlace
This layer contains the bottom side silk screen (see layer 21 for more details).
Layer 23 – tOrigins
This layer contains the top side component origins. It contains the origin cross for each component. Top side components can be moved or modifyed only if this layer is visible.
Layer 24 – bOrigins
This layer contains the bottom side component origins (see layer 22 for more details). Bottom side components can be moves only if this layer is visible.
Layer 25 – tNames
This layer contains the top side service print. It usualy contains the component names and may appear on the PCB as the silk screen.
Layer 26 – bNames
This layer contains the bottom side service print (see layer 25 for more details).
Layer 27 – tValues
This layer contains the top side component value. It usualy contains the component value and appears on the PCB as the silk screen and service print.
Layer 28 – bValues
This layer contains the bottom side component value (see layer 27 for more details).
Layer 29 – tStop
This layer contains the top side solder stop mask (solder mask). This is the nogo area for the green laque. Data is implicitly created for THT and SMD pads, and optionally VIAs (depending on settings).
Layer 30 – bStop
This layer contains the bottom side solder stop mask (see layer 29 for more details).
Layer 31 – tCream
This layer contains the top side solder paste data for SMD, normally used to make stencils for printing the paste to the board before assembly. Data is implicitly created with SMD pads. This area should be a little smaller that the solder stop mask because the green laque shouldn’t overlap solder areas.
Layer 32 – bCream
This layer contains the bottom side solder cream (see layer 31 for more details).
Layer 33 – tFinish
This layer is dedicate to special finishing process (plated gold, silver carbon. It may also be used if some of the pads need immersion gold plating. It is not automaticaly generated and it must be drawn by designer.
Layer 34 – bFinish
This layer contains the bottom side finish data (see layer 33 for more details).
Layer 35 – tGlue
This layer contains the top side glue mask. For wave soldering of SMD parts, they must be glued to the board first. Usually, one small dot in the center of chips, and several dots under IC packages are used. This layer must be drawn by the designer, normally when designing the libraries.
Layer 36 – bGlue
This layer contains the bottom side glue mask (see layer 35 for more details).
Layer 37 – tTest
This layer is the top side test and adjustment. It is dedicated to testpoint for ICT (In Circuit Test).
Layer 38 – bTest
This layer is the bottom side test and adjustment. It is dedicated to testpoint for ICT (In Circuit Test).
Layer 39 – tKeepout
This layer is the top side keepout area for components. Components should not be placed in this area (except for part ower of the area).
Layer 40 – bKeepout
This layer is the bottom side keepout area for components (see layer 39 for more details).
Layer 41 – tRestrict
This layer is the top side keepout area for tracks. Tracks should not be placed in this area.
Layer 42 – bRestrict
This layer is the bottom side keepout area for tracks (see layer 41 for more details).
Layer 43 – vRestrict
This layer is the keepout area for vias.
Layer 44 – Drills
This layer contains the conducting through holes. It is usually used for pads (of through hole components) and vias.
Layer 45 – Holes
This layer contains the non-conducting holes. It is usually used for s used for mounting holes.
Layer 46 – Milling
This layer is dedicated to milling. If the board manufacturer has to mill oblong holes, you have to draw the milling contour of oblong holes in this layer. Any other inner cutouts in the board are drawn in the same way. Draw the milling contours in this layer. Note that the board outline is not concerned and must be designed in the layer 20 (Dimension).
Layer 47 – Measures
This layer contains the measurement. It is not used during the manufacturing process, it is just display for information.
Layer 48 – Document
This layer contains the general documentation. Had here comments, or any usefull information that help understanding the design of the PDB.
Layer 49 – Reference
This layer contains the reference marks and is typicaly used for placing the fiducial marks. Fiducials are little target registration marks that are printed on PCBs, they are placed on the top copper layer (and bottom if you’re doing 2-layers) and allow the vision system of the pick and place to recognize where the PCB is at. They are not placed on the mask or silk because they are not as precisely aligned to the parts as the copper itself.
Here is a picture from Lady Ada (Adafruit company) that illustrate the automatic localization process of the fiducial marks:
Layer 51 – tDocu
This layer contains the top side part documentation. Place additional graphical information for the documentation here. This layer is not used to print onto the board itself, but is a supplement to the graphical presentation which might be used for printed documentation. Care must be taken in layer 21, tPlace, not to cover any areas that are to be soldered. A more realistic appearance can be given, however, in the tDocu layer, which is not subject to this limitation.
Layer 52 – bDocu
This layer contains the bottom side part documentation (see layer 51 for more details).
